Asic Design Verification Engineer jobs in San Francisco Bay Area
There are 8 open Asic Design Verification Engineer roles in San Francisco Bay Area on Linora right now, pulled daily from company career pages across Greenhouse, Ashby, Lever, and Workday. Typical pay runs $165k to $235k.
Updated 2026-07-27. Figures come from live job postings and refresh daily.
Pay on these live postings runs about $165k to $235k, across 7 roles that list a range.
- ASIC Design Verification EngineerWaymo · Mountain View, CA, USAWaymo is an autonomous driving technology company with the mission to be the world's most trusted driver. Since its start as the Google Self-Driving…$175,000 – $215,0005 days ago
- Sr. ASIC Design Verification Engineer (Silicon Engineering)SpaceX · Palo Alto, CASpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not…$175,000 – $280,0007 days ago
- ASIC Design Verification EngineerCisco · San Jose, California, USThe application window is expected to close on: 08/25/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of…$152,500 – $219,2001 month ago
- ASIC Design Verification EngineerCisco · San Jose, CACisco is a leading technology company that delivers silicon, optics, and hardware platforms powering core Switching, Routing, and Wireless products…$165K/yr - $241K/yr1 month ago
- ASIC Design Verification EngineerPalo Alto Networks · Hybrid - Santa ClaraPalo Alto Networks is dedicated to protecting the digital way of life through innovative technology. As a Design Verification Engineer on the ASIC…$106K/yr - $172K/yr2 months ago
- Senior ASIC Design Verification EngineerNvidia · US, CA, Santa ClaraNVIDIA is seeking a hardworking Senior ASIC Design Verification Engineer to help drive sign-off strategies for world's leading GPUs and SoCs. This…2 months ago
- ASIC Design Verification EngineerCisco · San Jose, California, USThe application window is expected to close on: 05/01/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of…$165,000 – $241,4002 months ago
- Sr. ASIC Design Verification Engineer (Starshield)SpaceX · Palo Alto, CASpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not…$170,000.00 - $235,000.003 months ago
Asic Design Verification Engineer pay distribution in San Francisco Bay Area
Base salary only (excludes equity and bonus), across 7 recent Asic Design Verification Engineer postings in San Francisco Bay Area that disclose pay.
Common questions
How many Asic Design Verification Engineer jobs are open in San Francisco Bay Area?
There are 8 open Asic Design Verification Engineer roles in San Francisco Bay Area on Linora right now, pulled daily from company career pages across Greenhouse, Ashby, Lever, and Workday.
How much does a Asic Design Verification Engineer earn?
The median Asic Design Verification Engineer salary is $170k to $260k per year, based on 16 live postings that list a range.
How often are Asic Design Verification Engineer jobs updated?
Daily. Linora reads roles straight from company career pages and drops listings that close, so the Asic Design Verification Engineer jobs shown are current rather than reposted or expired.